1. Field of the Invention
This invention relates to a semiconductor memory device, and more particularly to a refresh circuit for a dynamic random access memory (DRAM).
2. Description of the Prior Art
Each element of a memory cell array in DRAM, which is a memory cell, includes a charge-storage capacitor element and a MOS FET controlling input into and output from the capacitor element. The stored information is represented by the charge stored in the capacitor element. This charge will decay over time due to leakage current of MOS FET and the recombination on the surface of the semiconductor substrate. It therefore requires a process of refreshing periodically the stored information.
For accomplishing this refresh process at a high efficiency a number of refresh modes, have been utilized for example, the CAS before RAS refresh (CBR) mode in which refreshing is started by changing timings of external address signals CAS and RAS from those in the usual mode, and self-refresh mode in which, upon exceeding a predetermined wait time of the memory, all the memory cells are automatically refreshed at regular time intervals. In addition to these refresh modes, there is a kind of refresh process associated with read/write operation. In this operation, all memory cells connected to a selected word line supply the respective stored-contents to the associated bit lines connected to them, and the electric potentials of these bit lines are amplified by the sense amplifiers and restored as refreshed contents in the respective memory cells.
In such semiconductor memory devices, for the purpose of speed of operations, such as read/write operation except self-refresh mode, and refreshing in CBR mode, pulses of a relatively short active level duration (or pulse width) have been placed on the selected word line.
This method however may result in an insufficient stored charge quantity in the capacitor element of the memory cell. For example, the active level can not be maintained past the time point when the potential difference (restore level) between both terminals of the capacitor, which reflects its charge quantity, has reached as small as about 80% of the electric potential of the bit lines. In self-refresh mode, pulses of a relatively-long HIGH level duration are placed on a selected word line, and consequently the capacitor element of each memory cell is sufficiently charged with effects of going to relatively high restore level. This increases the duration of holding the data stored in the capacitor element, and accordingly permits refreshing at longer time intervals. By refreshing associated with regular read/write operations, a data-hold duration directly after this, is relatively short, and the time intervals of refreshing must be correspondingly short.
On the other hand, for example, when switched, directly after read or write operation has been completed, to the above-mentioned self-refresh mode, each memory cell holds the store data at the same low restore level as performed during the read/write operation. When such a situation remains, the read and write operation has been completed, and directly after this the switch to the above-mentioned self-refresh mode is performed. In such case it takes the same long time untill the first refreshing as in self-refresh mode where the data is stored at a high restore level in the memory cell, and within this time the charge stored in the capacitor element of the memory cell may decay away to an undetectable extent, probably resulting in producing an error in the storage contents.